1. Field of the Invention
The present invention relates to a method for manufacturing an SOI wafer, and more particularly to a method for manufacturing an SOI wafer for bonding two wafers to form a thin-film SOI layer by delamination and then further reducing a film thickness of the SOI layer.
2. Description of the Related Art
To reduce a parasitic capacitance and increase performances of a semiconductor device, a silicon-on-insulator (SOI) wafer having a single-crystal silicon layer formed on an insulator has been widely utilized. In recent years, a demand for a thin-film SOI having an SOI layer (a single-crystal silicon layer on an insulator) of 100 nm or below has been increased to fabricate a complete depletion layer type SOI device. That is because an increase in speed of the device by reducing a film thickness of the SOI layer can be expected.
As one of typical methods for fabricating an SOI wafer, there is an ion implantation/delamination method. As one of such methods, there is a Smartcut method (a registered trademark). According to this method, a hydrogen ion is implanted into a single-crystal silicon wafer or a single-crystal silicon wafer having an oxide film formed on a surface thereof (a donor wafer), this wafer is bonded to a support wafer (a handle wafer) and then heated to a temperature close to 500° C., the donor wafer is delaminated along a hydrogen ion implanted interface, a single-crystal silicon thin film is transferred to the handle wafer, and a heat treatment is subsequently performed at a high temperature (approximately 1100 to 1200° C.) by a method for polishing the surface roughened due to a heat treatment to provide a mirror surface or by using an inert gas such as argon or an inert gas having hydrogen added thereto, thereby smoothening the surface (see, e.g., Japanese Patent No. 3048201, Japanese Patent Application Laid-open No. H11-145438, and A. J. Auberton-Herve et al., “SMART CUT TECHNOLOGY: INDUSTRIAL STATUS of SOI WAFER PRODUCTION and NEW MATERIAL DEVELOPMENTS” (Electrochemical Society Proceedings Volume 99-3 (1999) pp. 93-106)).
However, this method has several problems. Since delamination of the donor wafer is performed by a heat treatment for generating small cavities called micro cavities on the hydrogen ion implanted interface, surface roughness occurs on the surface after delamination. According to Science of SOI, Chapter 2, Realize corporation, a difference of elevation of approximately 65 nm in terms of Peak to Valley (P-V) occurs even in a very narrow region of 1×1 μm. In light of an entire wafer region, it can be considered that a difference of elevation of 100 nm or above occurs. Therefore, a polishing amount of 100 to 150 nm or above is required in order to polish a surface of the SOI layer to eliminate irregularities on the surface of the SOI layer.
In general, accurately and uniformly polishing a surface to obtain a target thickness is difficult in a polishing process called CMP (chemical mechanical polishing). That is because constantly keeping conditions of a radial balance of various factors (e.g., a pressure or a supply amount of a slurry) concerning polishing or a polishing pad in a fixed state is difficult. For example, considering a case where an SOI layer having a film thickness of 250 nm immediately after donor wafer delamination to 100 nm, even if a radial fluctuation of a polishing stock removal is ±10%, a film thickness of a resultant SOI layer is 85 to 115 nm, thereby leading to a film thickness fluctuation of 30%.
On the other hand, in regard to the method for flattening a surface of an SOI layer based on a heat treatment, a lengthy heat treatment of 1100° C. or above is usually required in order to flatten irregularities on the surface of the SOI layer based on the heat treatment. Adding the heat treatment results in occurrence of a problem of, e.g., management of contamination due to a high-temperature process, an increase in cost, or a reduction in productivity. Further, in case of a substrate other than that formed of single-crystal silicon, e.g., a quartz substrate, a glass-transition temperature is near 1050° C., and flattening the surface based on a high-temperature heat treatment may be difficult. Therefore, this method is not desirable.
Furthermore, the method called an SiGen method for bonding two wafers and then mechanically performing delamination at a room temperature (see, e.g., Specification in U.S. Pat. No. 6,263,941, Specification in U.S. Pat. No. 6,513,564, and, Specification in U.S. Pat. No. 6,582,999) also has the same problem as that of the Smartcut method and others, and an SOI layer after delamination must be polished for approximately 0.1 μm to be removed.
Moreover, as a method for fabricating a thin-film SOI layer, there has been proposed, e.g., a PACE (Plasma Assisted Chemical Etching) method (see, e.g., Japanese Patent Application Laid-open No. H5-160074) for previously measuring a film thickness of an SOI layer after delamination and scraping the thin film while applying correction in accordance with a film thickness distribution thereof to fabricate a uniform thin-film silicon layer or a GCIB (Gas Cluster Ion Beam) method (see, e.g., Japanese Patent Application Laid-open No. H8-293483). It can be said that both the methods can meet an object of obtaining an SOI layer having high film thickness uniformity since etching can be performed while correcting a film thickness fluctuation by scanning an entire wafer surface with a plasma or an ion beam having a diameter of several mm to several cm.
However, these methods have a drawback. As different from the method of polishing the entire wafer surface at a time like CMP, a processing time becomes considerably long as compared with that of regular CMP and productivity is lowered since the entire wafer surface is scanned with a plasma nozzle or an ion beam having a small diameter. In recent years in particular, since an increase in a required diameter of an SOI wafer has been advanced, the problem is becoming more serious.